SBC-4P Information

*** Use the following information at your own risk.   I offer no guarantee that this information is without defects or design flaws.

This is what the SBC-4P verion looks like:

It has the 65816 microprocessor, running at 5 - 16 MHz. It can directly address the 512K of system RAM. During /RESET, the ATMega162 holds the /RES line low while it copies the desired program(s) to RAM. Once done, it releases the /RES and the 65816 starts executing instructions from RAM. The ATMega162 then becomes transparent while the 65816 is running.

The expansion port is buffered through the CPLD and provided decoding for up to four 32-byte I/O devices with dedicated interrupt for each. See the Daughter Board section for more details on the expansion port.

Other options in the SBC-4P board include either a standard RS-232 port or a Pololu USB Serial interface for the host terminal. The prototype shown above is using the Pololu module.

Here is a block diagram of the SBC-4P:

The system memory map is as follows:

$000000-$0001FF – RAM (default direct page and stack)
$000200-$00021F - IRQ Status Register (ISR)
$000220-$00023F - Write Protect Register (WPR)
$000240-$00025F - Interrupt Mask Register (IMR)
$000260-$00027F - 68C92 Dual-UART
$000280-$00029F - I/O Device 1
$0002A0-$0002BF - I/O Device 2
$0002C0-$0002DF - I/O Device 3
$0002E0-$0002FF - I/O Device 4
$000300-$00DFFF - System RAM
$00E000-$00FFFF - System RAM loaded with System Monitor during RESET
$010000-$07FFFF - System RAM Bank 1 thru 7 (onboard SRAM)
$080000-$47FFFF – 4MB Expansion Port

A jumper on the board will allow you to skip installing the onboard 512k SRAM and just running entirely from the Expansion module. In that case, the SRAM ends at $3FFFFF.

The IRQ Status Register (ISR) helps the interrupt handler decide which device is requesting service. By reading this register, it can selective jump to the proper interrupt handler. The Interrupt Mask register allows individual interrupt source to be enable or disabled.

The ISR and IMR will provide status and selection over the following interrupts:

BIT   Source
---   ------------
 7    68C92 UART
 6    I/O Device 4
 5    I/O Device 3
 4    I/O Device 2
 3    I/O Device 1
2-0   Not used

Reading a logic 1 in the ISR indicates an active interrupt. Its important to note that reading the ISR does not clear the interrupt, it only provides a status. Writing a logic 1 to the IMR enables that interrupt source, a logic 0 disables that source. The default state is all interrupts disabled. By using the IMR and/or the CLI/SEI instructions, total control over the interrupts can be attained.

The Write Protection will work with the memory expansion module by allowing 512K sections of the 4MB memory space to be write-protected. The goal is to be able to initially load large data tables and then protect them from accidental writes. Writing a 1 to an IMR bit will enable protection for that block. The default state is unprotected.

The Exar XR68C92 Dual UART provides a serial terminal interface for the user to access the system. Port 1 is connected to either a MAX-232 and DB9 RS-232 Connector, or to a Pololu USB Serial Adapter. The Pololu device has drivers for Windows, Linux, and MAC OSX-based platforms. The default Baud rate is 115200. The second port is connected directly to the Atmel ATMega162. This provides an inter-processor communications link that allows the user to set boot options, reload a boot image, or save a new boot image to either the onboard Flash memory store or to an I2C EEPROM memory module.

The ATMega162 has an 8k image store that it writes to RAM at $E000-$FFFF. It will be shipped with my 65816 System Monitor pre-installed but can be updated with user code. It will also be capable of reading and writing a 64kx8 serial EEPROM on the I2C port. This will be mapped into RAM from $0300-$FFFF. This EEPROM will be installed on a small board and can be easily unplugged and swapped to allow for multiple configurations. Users can develop their own custom OS and replace the SBCOS in Flash or store it to an optional I2C EEPROM. Boot options can be set to automatically boot from Flash or an I2C EEPROM. IF the latter is selected and the I2C Module us unplugged, the Flash image will be loaded. There will also be an Emergency Restore mode that will copy an image from the Serial terminal back into the 8K Flash, in the event a user accidentally overwrites the flash with a corrupt image. The Emergency image file will be provided in the support package.

Here is a picture of my prototype EEPROM module. The I2C line resistors will be on the main board in the final release.

The expansion port will be identical on both SBC-4B and SBC-4P and the daughter boards can be used on either platform. Keep in mind that the more I/O boards you add to the system, the more the expansion bus loading will be and maximum clock speed could be limited. I will release a few basic daughter boards supporting the most common I/O devices. User’s will be able to create their own custom daughter boards to suite their own specific needs. Full specifications covering the physical layout of the support holes and connector along with pin functions will be included in the support package.

These are the signals present on the expansion port:

1 - D0				2 - +5v
3 - D1				4 - /IO1 (Device select 1)
5 - D2				6 - +5v
7 - D3				8 - /IO2 (Device select 2)
9 - D4				10 - +5v
11 - D5				12 - /IO3 (Device select 3)
13 - D6				14 - -12v
15 - D7				16 - /IO4 (Device select 4)
17 - A0				18 - -12v
19 - A1				20 - /IRQ1 (Device Interrupt 1)
21 - A2				22 - +12v
23 - A3				24 - /IRQ2 (Device Interrupt 2)
25 - A4				26 - +12v
27 - /IRQ3 (Device Interrupt 3)	28 - R/W
29 - /IRQ4 (Device Interrupt 4)	30 - Gnd
31 - /RES (Input only)		32 - Gnd
33 - PHI2 (CPU clock)		34 – Gnd

All port logic connections are buffered through the 9572 CPLD on the SBC-4P. Each I/O device has 32 bytes of address space and one dedicated IRQ. Multiple I/O functions can be placed under a single I/O device as long as these resources can be shared. For instance, two 65C22’s could be placed on a daughter card and share one I/O Select as each uses 16 bytes of address space. The IRQ line from each can be tied through appropriate logic and presented to the dedicated IRQ line of that I/O device. It is also possible to allow one logical device to use more than one I/O Device select and IRQ. For instance, if an Ethernet card required 64 bytes of I/O, then you could use two I/O device selects using an AND gate to provide a single active-low Device select.

The Operating System consists of my SBCOS, which included a simple monitor (read/write/move/disassemble) and X-modem file transfer. The Terminal is set at 115200,N,8,1 and performs a 62KB transfer in about 16 seconds. This allows for timely program testing as well as downloading a more sophisticated OS after boot-up.


All info provided "as-is" and is Copyright 2010.
Last updated on Mar 12, 2012.