SPI Controller Device


65SPI

An SPI interface for the 65C02 family of microprocessors

This is the second version of my 65SPI using an Atmel ATF1504 CPLD.

I has now been tested on actual silicon and works per the datasheet!

This device was created to provide a basic SPI interface for the 65xx family of microprocessors.   Currently, the only way to provide SPI is to bit-bang it using a 6522 or equivalent device.   That uses a lot of microprocessor time and program space.   This device takes care of the data loading, shifting, clocking, and control - freeing the microprocessor for more important duties.   There is interrupt support to allow an ISR to handle the SPI interface.   The status register provides signals for polling if interrupts are not desired.

Features:

∑ CPU bus is compatible with 65C02 and 65C816 microprocessors
∑ Uses 4-byte memory map for host access to registers
∑ Operates as an SPI master
∑ SCLK derived from PHI2 or an External Clock source
∑ SPI Mode 0, 1, 2, 3 supported
∑ Shifts MSB first
∑ 8-bit Slave select register with 8 Slave Select outputs
∑ External slave select decoding can yield up to 255 addresses.
∑ Direct slave select decoding yields 8 devices
∑ Programmable interrupt
∑ Interrupt or polled transmit complete flags

Chip Layout:

                              M        /     E                    
                           V  I  n  n  R  G  X  R                
                  D  D  D  C  S  /  /  E  N  T  /                 
                  6  5  7  C  O  c  c  S  D  C  W                 
               ____________________________________              
              /   6  5  4  3  2  1 44 43 42 41 40  \             
         TDI |  7                                39 | PHI2       
          D4 |  8                                38 | TDO        
          D3 |  9                                37 | /CS2        
         GND | 10                                36 | CS1        
          D2 | 11                                35 | VCC        
         ss0 | 12            ATF1504             34 | A1         
         TMS | 13          44-Lead PLCC          33 | A0         
          D1 | 14                                32 | TCK        
         VCC | 15                                31 | ss6        
          D0 | 16                                30 | GND        
         ss1 | 17                                29 | ss7        
             |   18 19 20 21 22 23 24 25 26 27 28   |            
              \____________________________________/             
                 s  s  s  s  G  V  /  /  /  M  S                 
                 s  s  s  s  N  C  M  I  M  O  C                 
                 3  4  2  5  D  C  W  R  R  S  L                 
                                   R  Q  D  I  K                 
Pin Descriptions

A0-A1    Microprocessor address bus (input)
CS1      Chip select, active high (input) 
/CS2     Chip select, active low (input) 
D0-D7    Microprocessor data bus (bidirectional)
EXTC     External shift clock (optional input) 
GND      System ground 
/IRQ     Microprocessor interrupt line, active low (output) 
MISO     SPI Master In, Slave Out line (input) 
MOSI     SPI Master Out, Slave In line (output) 
PHI2     Microprocessor system clock (input) 
/RES     Microprocessor reset line, active low (input)
R/W      Microprocessor data read/write line (input) 
SCLK     SPI Shift Clock output 
SS0-SS7  Slave Select lines (outputs) 
VCC      System +5vdc 
n/c      No connection
/MRD     Memory read output PHI2 & RW - (65SPI does not use these)
/MWR     Memory write output PHI2 & !RW - (65SPI does not use these)

Register Address Map

CS1/CS2PHI2A1A0R/W=1 (Read)R/W=0 (Write)
0xxxxHi-ZHi-Z
x1xxxHi-ZHi-Z
xx0xxHi-ZHi-Z
10100SPI Data InSPI Data Out
10101SPI StatusSPI Control
1011xSlave SelectSlave Select
    x = donít care

See the full datasheet along with the source and Intel Hex object files here -> 65SPI v2


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All info provided "as-is" and is Copyright 2020.