SBC-3 Information

*** Use the following information at your own risk.   I offer no guarantee that this information is without defects or design flaws.

SBC-3 is my latest design. It is now complete. Thanks to those who participated in the bulk order!

This is what it looks like:

Here's the block diagram:

It has the 65816 microprocessor, running at 7.159 MHz (NTSC, PAL is 8 MHz.)   It can directly address the 512K of system RAM.   During /RESET, the CPLD holds the /RES line low while it copies the EEPROM to RAM from $08000 to $0FFFF.   Once done, it releases the /RES and the 65816 starts executing instructions from RAM.   The EEPROM is placed in low-power standby while the MPU is running.

The video system uses the transparent DMA method.   During the low phase of PHI2, the CPLD accesses RAM and outputs pixel data to the video system.   During the high phase of PHI2, the CPLD lets the MPU access RAM.

I was inspired to use this video display hardware when I found this General Purpose Display Controller on the Internet.

The Video output is 320x200 pixels, using 8 bits per pixel (256 colors).   This uses 64000 bytes for an entire screen. The CPLD holds a 3 bit video display register that selects which 64k byte block of RAM to display.   At start-up, the Video display register is set to 001 ($10000-1F9FF).   The Monitor will use memory from $1FA00 to $1FDE7 is used for text data (40 characters x 25 lines).   Text is generated using software to write text as graphical data.   The default text font is 8x8 pixels per character. Address $1FDE8 to $1FFFF is not used by the video system and can be used for general storage.   To change the Video Display Register, you write the block number ($00 to $07) to address $00230.   Reading that address will give you the current block in bits 0-2.   bit 7 contains the vertical sync flag; 1 = vertical sync, 0 = no vertical sync.   bits 3-6 are not used.   Changes to the Video Display Register will take affect during the next vertical refresh, preventing flicker.   There is also a Video Interrupt pin that is connected to the NMI interrupt, and when enabled in software, provides an interrupt during the 3 vertical sync lines.

The pixel data is formatted as BBGGGRRR (Bits 0-2 are Red, 3-5 are Green, and 6-7 are Blue).   A resistor network forms a voltage divider to convert the bits to analog votages from 0 to 0.7V for each color.   These are fed into the AD724 to generate the color display.

The IO Block has two 65C22's available for general purpose IO.   In addition, a modified version of my 65SPI chip provides 7-192 addressable SPI ports for user IO.

The system memory map is as follows:

$00000-$0000F - VIA 1 I/O
$00010-$0001F - VIA 2 I/O
$00020-$00027 - SPI I/O
$00028-$0002F - unmapped I/O Space
              $00030 - Video Display Register I/O
$00031-$07FFF - System RAM
$08000-$0FFFF - System RAM loaded with contents of the EEPROM during RESET - Software-selectable Write Protect
$10000-$1FFFF - System RAM - Default Video display block
$20000-$7FFFF - System RAM

The modified 65SPI provides device selects and IRQ handling for the VIA's as well as SPI functions.   SS7 can be used as the External SCLK input by toggling the ECE bit high (default value).   When ECE is low, SS7 functions as an output and clocking is from PHI2 clock.

The SPI Register map is here:
AddressR/W=1 (Read)R/W=0 (Write)
$00020SPI Data InSPI Data Out
$00021SPI StatusSPI Control
$00022SCLK DivisorSCLK Divisor
$00023Slave SelectSlave Select
$00024Interrupt Status High-Z
Addresses $00025-$00027 are duplicates of $00024.

The Interrupt Status Register provides the status of the SPI Interrupt and both VIA interrupts: Bit 7 = SPI, Bit 6 = VIA1, Bit 5 = VIA2. SS6 will be used by an ATMega8 controller to provide RS-232 and PC Keyboard connections. That leaves SS0-SS5 (and SS7 if using PHI2 clocking) for user devices.   There are 7 ports for single SPI devices or the extension port can be used to decode more SPI ports on another board.   The acutal SPI functions operate as described in the 65SPI datasheet in the Downloads section.

The ATMega8 hosts a PC keyboard interface and RS-232 port via SS6 on the 65SPI.   It will use an 8MHz internal clock so its SPI interface will max out at 2MHz.   It will handle the keyboard scancode to ASCII conversion and will provide RS-232 data transfer. User can select from baud rates (2400,4800,9600,19200,38400); 7 or 8 data bits; 1 or 2 stop bits; and odd, even or no parity.

I am including a simple Monitor that supports keyboard input, text and graphics output, and xmodem transfers via RS-232 for PC-based storage.   The monitor source and binaries are included in the SBC-3 Support File.

For those using the SPI to IDE Interface, I also have the DiskOS available.

For those interested in programming in "C", check out the SBC-3 Upgrades for information on using CC65 targeted for the SBC-3.


All info provided "as-is" and is Copyright 2020.
Last updated on May 11, 2020.